In a transistor used in a semiconductor integrated circuit, a current (leak current) flows even in a state in which no operation is carried out, consuming electric power. Because of this, a method has been adopted, which electrically disconnects the power source of a circuit not in operation in order to reduce the leak current. FIG. 1 shows an example of a configuration of an electronic device system including a conventional image processing LSI 6. In image processing LSI 6, a first circuit part 7 and a second circuit part 8 are provided. First circuit part 7 is a memory (hereinafter, explained as SRAM), such as SRAM, to save a decryption key necessary to decode encrypted data, or a circuit, such as a timer, which is always in operation, and it is necessary for first circuit part 7 to be in an operating state or in a data holding state at all times. On the other hand, second circuit part 8 is a logic circuit for image processing etc., and is a circuit that may be put into a suspended state without the need to supply power when not in operation.
First circuit part 7 and second circuit part 8 are coupled to external power source lines 11 and 12 via internal power source lines 13 and 14 and a power source is supplied from an external power source supply part 9 via these power source lines. A low potential side power source GND is common. When second circuit part 8 is not in operation, no power source is necessary and therefore a switch SW1 is provided within power source supply part 9, which may be controlled to turn on/off by a control signal S1 from a CPU 1, and thus the supply of power source may be controlled. On the other hand, first circuit part 7 is always supplied with a power source in order to hold stored data. CPU 1 mounted on an LSI chip different from image processing LSI 6 is coupled to image processing LSI 6 and transmits image data or processing programs. CPU 1 is coupled with an operation part 4, a display part 3, and an external memory 2 via a bus 5, and thus, the transmission of data with any of the devices is enabled.
The control of SW1 by CPU1 when a user decodes image data in memory 2 and displays it on display part 3 in this system is explained. As an initial state, in first circuit part 7 of image processing LSI 6, data necessary for decode processing is saved. For example, a decryption key necessary to decode encrypted data is saved. It is assumed that SW1 is electrically disconnected (opened) because the data in second circuit part 8 does not need to be saved.
When a user presses a button of operation part 4, a control signal to instruct activation is sent from the operation part to CPU 1. CPU 1 sends power source supply control signal S1 to power source supply part 9 in order to close SW1. Upon receipt of the power source supply control signal, power source supply part 9 closes SW1. CPU 1 transfers image data and a processing program from memory 2 to first circuit part 7 of image processing LSI 6 and commands execution of the processing program. In image processing LSI 6, second circuit part 8 reads the program, the image data, and the decryption key from first circuit part 7 to carry out processing and writes image data after the processing in first circuit part 7. The image data after the processing is sent to display part 3 from first circuit part 7. When all of the processing is completed, image processing LSI 6 sends a control signal indicative of the completion of the processing to CPU 1. CPU 1 sends power source supply control signal S1 to power source supply part 9 in order to open SW1. Upon receipt of power source supply control signal S1, power source supply part 9 opens SW1.
As explained above, in an electronic circuit system having a multi-power source LSI, the circuit within the LSI is divided into a plurality of circuit parts and the supply of power source to each circuit part is carried out via distinct power lines and thus it may be possible to terminate the supply of power source from the power source supply part to a circuit part not in operation within the LSI. In order to separate the supply of power source to each circuit part, an electrode pad to be coupled to power source line 13 of first circuit part 7 and an electrode pad of the LSI package to be coupled to power source line 11 are coupled by a boding wire etc., and similarly, an electrode pad to be coupled to power source line 14 of second circuit part 8 and an electrode pad of the LSI package to be coupled to power source line 12 are coupled by a boding wire etc.
Patent document 1 (Japanese Unexamined Patent Publication (Kokai) No. H5-291368) and patent document 2 (Japanese Unexamined Patent Publication (Kokai) No. 2005-109238) describe a configuration in which the circuit within an LSI is divided into a plurality of circuit parts and the supply of power source to each circuit part is carried out via distinct power source lines. Further, patent documents 1 and 2 describe a configuration in which switches that couple a power source line of a plurality of circuit parts of an LSI to another are provided within the LSI. In this LSI, when a rated voltage is applied to the LSI, the switch is put into a state of out of conduction and normal operation is carried out and when a voltage that exceeds the rating is applied at the time of test, the switch is brought into conduction and thus the number of probes that are caused to come into contact with the electrode pad at the time of the test of LSI may be reduced.
Patent document 3 (Japanese Unexamined Patent Publication (Kokai) No. 2005-101325 describes a configuration in which a switch that couples an input terminal of an external power source of an LSI to another is provided and when a voltage that exceeds the rating, such as a surge voltage, is input, the switch is brought into conduction and thus a raise in voltage is suppressed.
However, none of patent documents 1 to 3 describe a configuration in which the supply of power source to part of the circuit within the LSI is terminated.
Patent document 1: Japanese Unexamined Patent Publication (Kokai) No. H5-291368
Patent document 2: Japanese Unexamined Patent Publication (Kokai) No. 2005-109238
Patent document 3: Japanese Unexamined Patent Publication (Kokai) No. 2005-101325